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logic gate

英 [ˈlɒdʒɪk ɡeɪt]

美 [ˈlɑːdʒɪk ɡeɪt]

n.  逻辑门,逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)

牛津词典

    noun

    • 逻辑门,逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)
      an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .

      英英释义

      noun

      • a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
          Synonym:gate

        双语例句

        • Diode transistor logic gate
          二极管晶体管逻辑门
        • Implication Logic Function and Implication Logic Gate
          蕴函逻辑函数和蕴函逻辑门的研究
        • Based on the double parameter logic gate control, a new fuzzy control logic is presented and a two-stage fuzzy logic controller based on wheel angle acceleration is designed.
          文中以双参数逻辑门限控制方法为基础提出了新的模糊控制逻辑,设计了基于车轮角加速度的两级模糊防抱控制器;
        • Boolean logic operation follows the Boolean logic, such as this logic gate is called Boolean logic gate.
          逻辑操作遵循布尔逻辑,这样的逻辑门就称为布尔逻辑门。
        • Josephson junction logic gate
          约瑟夫逊结逻辑门电路
        • Use the quantum logic gate for implementing multi-purpose quantum cloning machine.
          利用通用量子门实现多用途量子克隆机的方案。
        • And the new applications in the fields of logic gate and radio-on-fiber system are presented.
          并介绍SOA在放大、波长变换、光逻辑门和无线光通信等方面的应用。
        • Threshold Logic Gate ( TLG) is receiving much attention because of its logic versatility and functionally complete.
          阈值逻辑门由于具有强大的逻辑功能且独自构成完备集而备受关注。
        • This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure.
          本文介绍了一种新的数码乘法器结构:采用一级逻辑门结构实现阵列式数码乘法器,并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。
        • After study a series array multipliers algorithms and architectures,. the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill.
          本文研究讨论了各种不同阵列乘法器的结构和原理,并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。